AMD Alveo UL3524 Application Accelerator

$215,000.00

AMD Alveo UL3524 Application Accelerator

  • Mfg Part No: XLN-A-UL3524-P16G-PQ-G | A-UL3524-P16G-PQ-G
  • High-performance application accelerator designed to enhance computing capabilities.
  • Optimized for various workloads, providing efficient processing power for demanding applications.
  • Advanced architecture ensures reliability and speed, making it a valuable addition to any computing environment.

HS Code: 85176290 | 84715000

Country Of Origin: Taiwan, China

Resources:

Description

  • The Alveo UL3524 card is powered by a purpose-built FPGA for electronic trading, based on the production-proven 16nm UltraScale+ architecture. The device features a breakthrough transceiver architecture that achieves less than 3ns transceiver latency† and is 7X faster than previous generation FPGA technology††, delivering high-performance trade execution.
  • Equipped with 4 network ports at 10/25Gb/s data rates, the card comes in a Full-Height,  ¾ Length (FH¾L) PCIe® form factor, deployable in 1U, 2U, and 4U servers. The Alveo UL3524 card is now shipping and in production deployment.

Features:

  • Purpose-Built for Ultra-Low Latency (ULL) Performance
  • Custom FPGA device and new transceiver architecture for fast trade execution
  • Less than 3ns transceiver latency and 7X performance vs. previous generation
  • Hardware Flexibility and AI-Enabled Trading Strategies
  • FPGA fabric to accelerate diverse strategies and evolving algorithms
  • Open-source PyTorch development flow available for low latency AI
  • For Diverse FinTech Applications
  • For ULL algorithmic trading, pre-trade risk analysis, and data delivery services
  • Enabling an ecosystem of custom FinTech solutions and ULL infrastructure
  • FPGA Accelerator for Ultra-Low Latency Trading ALVEO™ UL3524 ACCELERATOR CARD

Key Applications:

  • TARGET USERS: Proprietary Traders | Hedge Funds | Market Makers | Brokerages | Market Data Vendors | Exchanges
  • USE CASES: Ultra-Low Latency Trading | Pre-Trade Risk Analysis | Market Data Delivery & Distribution

Key Technical Specifications: 

  • Processor: Virtex UltraScale+ FPGA (XCVU2P-FSVJ2104-3-E).
  • Logic Resources: 787K LUTs, 1,722K Registers, 1680 DSP Slices.
  • Memory: 16GB DDR4 (64b + 8b ECC at 2666 MT/s), 72MB QDR II+ (550 MHz).
  • Networking: 4 x QSFP-DD ports supporting 10Gb/25Gb Ethernet.
  • Latency: less than 3 ns (transceiver latency).
  • PCIe Interface: Gen4 x8.
  • Power: 180W (Card Load), 125W (TDP), 12V PCIe AUX 2×4 input.
  • Cooling: Passive.
  • Dimensions: Full-height, 3/4 length, single slot.
  • Clock Speed: 644 MHz (for market data streaming).